The dimensions of electronic circuit elements have decreased rapidly over the past half century. Familiar circuit elements, including resistors, capacitors, inductors, diodes, and transistors that were once macroscale devices soldered by hand into macroscale circuits are now fabricated at sub-microscale dimensions within integrated circuits. Photolithography-based semiconductor manufacturing techniques can produce integrated circuits with tens of millions of circuit elements per square centimeter. The steady decrease in size of circuit elements and increase in the component densities of integrated circuits have enabled a rapid increase in clock speeds as which integrated circuits can be operated as well as enormous increases in the functionalities, computational bandwidths, data-storage capacities, and efficiency of operation of integrated circuits and integrated-circuit-based electronic devices.
Unfortunately, physical constraints with respect to further increases in the densities of components within integrated-circuits manufactured using photolithography methods are being approached. Ultimately, photolithography methods are constrained by the wave length of radiation passing through photolithography masks in order to fix and etch photoresist and, as dimensions of circuit lines and components decrease further into nanoscale dimensions, current leakage through tunneling and power-losses, due to relatively high resistances of nanoscale components are providing challenges with respect, to further decreasing component sizes and increasing component densities by traditional integrated-circuit-manufacturing and design methodologies. These challenges have spawned entirely new approaches to the design and manufacture of nanoscale circuitry and circuit elements. Research and development efforts are currently being expended to create extremely dense, nanoscale electronic circuitry through self-assembly of nanoscale components, nanoscale imprinting, and other relatively new methods. In addition, new types of circuit elements that operate at nanoscale dimensions have been discovered, including memristive switching materials that can be employed as bistable nanoscale memory elements. Unfortunately, memristive switching materials, and other candidate bistable-memory-element materials, which feature non-linear responses to applied voltage, temperature, and other forces and gradients that are applied to change the state of the materials, often exhibit relatively broadly distributed, asymmetrical probability density functions (“PDFs”) that characterize the probabilities that a memory element switches with respect to different durations of time that the switching force or gradient is applied. The asymmetrical PDF may feature a relatively long tail, corresponding to the fact that the force or gradient may need to be applied for a significantly greater period of time, to ensure switching, than the average time for switching. Alternatively, the PDF characterizes the switching behaviors of a large number of memory elements, with the long tall corresponding to a small fraction of the large number of memory elements which switch at significantly longer durations of application of the force or gradient than the majority of the large number of memory elements. This fact, in turn, entails significantly decreased operational bandwidths and/or reliability with respect to theoretical devices with narrowly distributed, symmetrical PDFs, for which the time that a force or gradient needs to be applied in order to ensure switching up to a probability corresponding to a maximum tolerable bit error rate is not significantly greater than the average application time at which switching occurs. Theoreticians, designers, and developers of memory devices and other data-storage devices based on non-linear data-storage materials, such as memristive materials, continue to seek methods and device architectures that ameliorate the asymmetrical, broadly-distributed switching-time characteristics of certain of these devices.